Program No. 1
1.Given a 4-variable logic expression, simplify it using appropriate technique and simulate the
same using basic gates.
b) Simplification of 4 variable SOP expression:
Y= f(a,b,c,d) = Σm(2,3,4,5,6,7,9,10,11,14,15).
K-MAP: TRUTH TABLE:
EQUATION:
Y= c + a`b + ab`d
LOGIC DIAGRAM:
a
b
c
d
Y
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
PROGRAM:
module eqn2 (a,b,c,d,Y);
input a,b,c,d;
output Y ;
assign Y= ( c | (~a&b) | ( (a&~b& d) ));
endmodule
EXERCISE:
c) Simplification of 3 variable POS expression
Y= f(a,b,c) = Î M(0,1,2,4,5).
d) Simplification of 4 variable POS expression
Y= f(a,b,c,d) = Î M(2,3,4,5,6,7,8,12,13,14,15).
Program No. 2
2.Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and
Full Subtractor.
i) HALF ADDER
Half adder is an arithmetic combinational logic circuit designed to perform addition of two
single bits. It contains two inputs and produces two outputs Sum and Carry.
BLOCK DIAGRAM: TRUTH TABLE :
a Sum
b Cout
K –MAPS:
Sum: Cout:
EQUATIONS:
Sum= a ⊕ b
Cout= a.b
Input
Output
a
b
Sum
Cout
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
HALF
ADDER
LOGIC CIRCUIT:
PROGRAM:
module half_add(a,b, Sum,Cout);
input a,b;
output Sum,Cout;
assign Sum= a ^b;
assign Cout = a & b;
endmodule
a
b
Sum
Cout
i) FULL ADDER
Full adder is an arithmetic combinational logic circuit that performs addition of three single
bits. It contains three inputs (a, b, C
in
) and produces two outputs (Sum and C
out
) where, C
in
is
Carry In and C
out
is Carry Out.
BLOCK DIAGRAM: TRUTH TABLE:
a SUM
b
Cin Cout
K –MAPS:
Sum: Cout:
EQUATIONS:
Sum = a ⊕ b⊕ Cin
Cout = a b + b Cin + a Cin
Input
Output
a
b
Cin
Sum
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
FULL
ADDER
LOGIC CIRCUIT:
PROGRAM:
module full_add(a,b,Cin,Sum,Cout);
input a,b,Cin;
output Sum,Cout;
assign Sum= a ^b^Cin;
assign Cout = (a&b) | (b&Cin) | (a&Cin);
endmodule
i) HALF SUBTRACTOR
Half subtractor is a combinational logic circuit designed to perform the subtraction of two
single bits. It contains two inputs (a and b) and produces two outputs (Difference and Borrow-
out).
BLOCK DIAGRAM: TRUTH TABLE:
a Diff
b Bout Bout
K –MAPS:
Diff: Bout:
EQUATIONS:
Diff = a ⊕ b
Bout= a`b
LOGIC DIAGRAM:
Bout
a
b
Diff
Input
Output
a
b
Diff
Bout
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
HALF
SUBTRACTOR
PROGRAM:
module half_sub(a,b, Diff,Bout);
input a,b;
output Diff,Bout;
assign Diff= a ^ b;
assign Bout = ~a & b;
endmodule
i) FULL SUBTRACTOR
Full subtractor is a Combinational logic circuit designed to perform subtraction of three single
bits. It contains three inputs(a, b, B
in
) and produces two outputs (Diff, B
out
) where B
in
is
Borrow-In and B
out
is Borrow-Out.
BLOCK DIAGRAM: TRUTH TABLE :
a Diff
b
Bin Bout
K –MAP:
Diff: Bout:
Input
Output
a
b
Bin
Diff
Bout
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
FULL
SUBTRACTOR
LOGIC CIRCUIT:
PROGRAM:
module full_sub(a,b,Bin, Diff,Bout);
input a,b,Bin;
output Diff, Bout;
assign Diff= a ^b ^Bin;
assign Bout = (~a & b) | (~a & Bin) | (b & Bin)
endmodule
EQUATIONS:
Diff = a ⊕ b ⊕ Bin
Bout = a` b +a` Bin + b Bin
3.Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioural
model.
Structural Model
module p3structural(a,b,c,d,e,y);
input a;
input b;
input c;
input d;
input e;
output y;
wire Y1,Y2;
and G1(Y1,a,b);
and G2(Y2,c,d,e);
or G3(Y,Y1,Y2);
endmodule
Data Flow Model
module p31(a,b,c,d,e,y);
input a;
input b;
input c;
input d;
input e;
output y;
wire Y1,Y2;
assign Y1=a & b;
assign Y2= c&d&e;
assign y= Y1|Y2;
endmodule
Behavioral Model
module p3behavioral(a,b,c,d,e,y);
input a;
input b;
input c;
input d;
input e;
output y;
reg y;
always @(a,b,c,d,e)
begin
y= (a & b) | (c & d &e);
end
endmodule
4.Design a 4-bit full adder and subtractor and simulate the same using basic gates.
Full adder
BOOLEAN EXPRESSIONS:
sum= A ⊕ B ⊕ C
carry=A B + B C + A C
TRUTH TABLE:
Full adder: -
Step 1
module p2updated(a,b,sum,carry,c);
input [3:0] a;
input [3:0] b;
output [3:0] sum;
output carry;
input c;
wire c1,c2,c3;
fa FA0(sum[0],c1,a[0],b[0],c);
fa FA1(sum[1],c2,a[1],b[1],c1);
fa FA2(sum[2],c3,a[2],b[2],c2);
fa FA3(sum[3],carry,a[3],b[3],c3);
endmodule
Step 2
(create the file fa.v under the main module p2updated.v)
i) right click on main module p2updated.v
ii) select new source ->Verilog module ->enter file name as fa.v
iii) fa.v sub module gets created under the main module as seen in the process window
iv) type the code in the sub module fa.v and save.
v) compile both the main module p2updated.v and sub module fa.v
module fa(sum,carry,a,b,cin);
output sum;
output carry;
input a;
input b;
input cin;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10;
not G1(w1,a);
not G2(w2,b);
not G3(w3,cin);
and G4(w4,a,b,cin);
and G5(w5,w1,w2,cin);
and G6(w6,w1,b,w3);
and G7(w7,a,w2,w3);
and G8(w8,a,b);
and G9(w9,b,cin);
and G10(w10,a,cin);
or G11(sum,w4,w5,w6,w7);
or G12(carry,w8,w9,w10);
endmodule
Step2 output
DDCO LAB Programs
5.Design Verilog HDL to implement Decimal adder.
This Verilog module, "DecimalAdder," takes two 4-bit decimal inputs A and B and produces
a 4-bit sum (Sum) and a carry-out (CarryOut) output. The logic inside the "always" block
performs decimal addition with carry propagation, and it also handles the case when the result
is greater than 9. In such cases, it adds 6 to the result and updates the carry accordingly.
module p5deci(a,b,sum,cout);
input [3:0] a;
input [3:0] b;
output [3:0] sum;
output cout;
reg [3:0] sum;
reg cout;
always@ (a,b)
begin
{cout,sum} = a+b;
if(a>9 || b>9 || sum>9)
begin
{cout,sum} = sum+6;
end
end
endmodule
Example:
1110 + 1110 = 11100
Here carry is 1 and sum is 1100. Now add 6 to sum.
1100 + 0110 = 10010 and the output to check is sum as 0010 and carry is 1.
6.Design Verilog program to implement Different types of multiplexer like 2:1,
4:1 and 8:1.
Truth Table:
The logical expression of the term Y is as follows: Y=S
0
'.A
0
+S
0
.A
1
module p621(y,A0,A1,S0);
output y;
input A0;
input A1;
input S0;
reg y;
always @ (A0,A1,S0)
begin
y=((~S0 & A0)|(S0 & A1));
end
endmodule
Truth Table:
The logical expression of the term Y is as follows:
Y=S
1
' S
0
' A
0
+S
1
' S
0
A
1
+S
1
S
0
' A
2
+S
1
S
0
A
3
Verilog code:
module p641(y,A0,A1,A2,A3,S0,S1);
output y;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
reg y;
always @ (A0,A1,A2,A3,S0,S1)
begin
y= (~S0 & ~S1 & A0) | (S0 & S1 & A1) | (S0 & ~S1 & A2) | (S0 & S1 & A3);
end
endmodule
Truth Table:
The logical expression of the term Y is as follows:
Y=S
0
'.S
1
'.S
2
'.A
0
+S
0
.S
1
'.S
2
'.A
1
+S
0
'.S
1
.S
2
'.A
2
+S
0
.S
1
.S
2
'.A
3
+S
0
'.S
1
'.S
2
A
4
+S
0
.S
1
'.S
2
A
5
+S
0
'
.S
1
.S
2
.A
6
+S
0
.S
1
.S
3
.A
7
Verilog Code:
module p681(Y,A0,A1,A2,A3,A4,A5,A6,A7,S0,S1,S2);
output Y;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
input S0;
input S1;
input S2;
reg Y;
always @ (A0,A1,A2,A3,A4,A5,A6,A7,S0,S1,S2)
begin
y= (~S0 & ~S1 & ~S2 & A0 ) |
(~S0 & ~S1 & S2 & A1) |
(~S0 & S1 & S2 & A2) |
( ~S0 & S1 & S2 & A3) |
(S0 & ~S1 & ~S2 & A4) |
(S0 & ~S1 & S2 & A5) |
(S0 & S1 & ~S2 & A6) |
(S0 & S1 & S2 & A7) ;
end
endmodule
7.Design Verilog program to implement types of De-Multiplexer.
The logical expression of the term Y is as follows:
Y
0
=S
0
'.A
Y
1
=S
0
.A
Logical circuit of the above expressions is given below:
module P712(A,Y0,Y1,S0);
input A;
output Y0;
output Y1;
input S0;
reg Y0,Y1;
always @ (S0,A)
begin
Y0=(~S0 & A);
Y1=(S0 & A);
end
endmodule
1×4 De-multiplexer:
The logical expression of the term Y is as follows:
Y0=S1' S0' A Y2=S1 S0' A
Y1=S1' S0 A Y3=S1 S0 A
module P714(A,S0,S1,Y0,Y1,Y2,Y3);
input A;
input S0;
input S1;
output Y0;
output Y1;
output Y2;
output Y3;
reg Y0,Y1,Y2,Y3;
always @ (S0,S1,A)
begin
Y0=(~S0 & ~S1 & A);
Y1=(~S0 & S1 & A);
Y2=(S0 & ~S1 & A);
Y3=(S0 & S1 & A);
end
endmodule
1×8 De-multiplexer
The logical expression of the term Y is as follows:
Y
0
=S
0
'.S
1
'.S
2
'.A Y
1
=S
0
.S
1
'.S
2
'.A Y
2
=S
0
'.S
1
.S
2
'.A Y
3
=S
0
.S
1
.S
2
'.A
Y
4
=S
0
'.S
1
'.S
2
A Y
5
=S
0
.S
1
'.S
2
A Y
6
=S
0
'.S
1
.S
2
A
Y
7
=S
0
.S
1
.S
3
.A
module P718(A,S0,S1,S2,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7);
input A;
input S0;
input S1;
input S2;
output Y0;
output Y1;
output Y2;
output Y3;
output Y4;
output Y5;
output Y6;
output Y7;
reg Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
always @ (S0,S1,S2,A)
begin
Y0=(~S0 & ~S1 & ~S2 & A);
Y1=(~S0 & ~S1 & S2 & A);
Y2=(~S0 & S1 & ~S2 & A);
Y3=(~S0 & S1 & S2 & A);
Y4=(S0 & ~S1 & ~S2 & A);
Y5=(S0 & ~S1 & S2 & A);
Y6=(S0 & S1 & ~S2 & A);
Y7=(S0 & S1 & S2 & A);
end
endmodule
8. Verilog program for implementing various types of Flip-Flops
such as SR, JK and D.
SR Flip Flop
An SR Flip Flop is short for Set-Reset Flip Flop. It has two inputs S(Set) and R(Reset) and
two outputs Q(normal output) and Q'(inverted output).
module SR_flipflop (
input clk,
input s,r,
output reg q,
output q_bar
);
always@(posedge clk) begin
case({s,r})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= 1'bx; // Invalid inputs
endcase
end
end
assign q_bar = ~q;
endmodule
J K FlipFlop
module jk_ff ( input j, input k, input clk, output q);
reg q;
always @ (posedge clk)
case ({j,k})
2'b00 : q <= q;
2'b01 : q <= 0;
2'b10 : q <= 1;
2'b11 : q <= ~q;
endcase
endmodule
D FlipFlop
