Step 2
(create the file fa.v under the main module p2updated.v)
i) right click on main module p2updated.v
ii) select new source ->Verilog module ->enter file name as fa.v
iii) fa.v sub module gets created under the main module as seen in the process window
iv) type the code in the sub module fa.v and save.
v) compile both the main module p2updated.v and sub module fa.v
module fa(sum,carry,a,b,cin);
output sum;
output carry;
input a;
input b;
input cin;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10;